Overview of the ieee P standard. Conference Paper (PDF Available) · January with 2, Reads. DOI: /TEST · Source: IEEE. IEEE P defines a mechanism for the test of digital aspects of core designs within a System-on-. Chip (SoC). This mechanism is a scaleable standard. standard IEEE , titled “Standard Testability method for Embedded Core- based Integrated. Circuits”. IEEE P defines a mechanism for the test of.
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This application is a divisional of prior application Ser. Which is a divisional of prior application Ser. This application is related to nonprovisional patent application Ser. This disclosure relates in general to integrated circuit design and testing, and in particular to an improved test interface and architecture that may be included in intellectual property core circuits and integrated circuits. Today large system-on-chips SOC are being designed that include a myriad of different types of complex functional circuits.
Each IC test standard has its own test interface and architecture, and unique testing p1500.
Thus an IC may require both test standards to be implemented to achieve an overall testing goal. Having to include both test standards in ICs can be costly in circuit area overhead and test complexity. To facilitate the understanding of the present disclosure, an overview of two test standards to be combined is provided.
The test interface and architecture are well known and were standardized in as IEEE Standard While initially developed as an IC test standard for primarily supporting board level IC to IC interconnect testing, this standard has evolved into additional uses and formed the basis for a family of additional IEEE standards.
Overview of the IEEE P standard – Semantic Scholar
The test architecture includes an instruction register and a set of selectable data registers. As seen in FIG.
Stanrard naming of the data registers in FIG. As seen, a gating circuit receives input from the instruction register to allow the data register control bus from the TAP to pass through the gating circuit and be output on bus to operate a selected data register. The gating circuit is typically viewed as being part of the instruction register and is shown in FIG. The data registers also receive mode control input from the instruction register to place them in various modes of operation. The operation of the TAP controller is well known.
The Select signal is used to select either the instruction register or selected data register to be coupled to TDO. The TAP state bus is useful in controlling synchronous instruction and data register designs and is therefore shown as being part of the instruction and data control buses andrespectively.
The instruction register comprises a shift registeran update p15000and an instruction decode logic The shift register comprises serially connected scan cells that operate to capture and shift data from TDI to TDO. The update register comprises a flip-flop or latch for each shift register scan cell After capturing and shifting, the TAP outputs control UpdateIR to cause the latches of update register to load data from the scan cells The latched data is output from the update register to the decode logic, where it is decoded into control output bus p100, among other things, drives buses and While not shown, both the scan cell and update latch can be reset by the reset output from the TAP.
The synchronous instruction register design style differs from the gated instruction design style oeee that the shift register is comprised of scan cells which operate from the free running TCK input, not the ClockIR input of FIG.
Overview of the IEEE P1500 standard
The operation of the update register and decode logic is the same as describe in FIG. As with the FIG. Data register 1 comprises serially connected boundary scan cells each having an scan cell operable to capture data from the IN input and to shift data from TDI to TDO, and an update latch operable to load data from the scan cell.
If selected by the instruction in the instruction stanard, gates – within gating circuit are enabled by a signal on bus to couple the Stansard ClockDR, ShiftDR, and UpdateDR outputs to data register 1 ‘s Clock- 1Shift- 1and Update- 1 inputs, respectively. This enables scan access of data register 1. After capturing and shifting, the TAP shandard control UpdateDR to cause the update latches of the boundary stxndard cells to load data from the scan cells If data register 1 is in test mode, the Mode- 1 input from instruction register bus will be set to cause the data in update latch to be output from data register It is important to note p1500 later reference in this and following timing ieeee that the dotted box area beginning with A and ending with B sandard when the TAP is in the ShiftDR state.
Data register 2 comprises serially connected boundary scan cells each having an scan cell operable to capture data from the IN input and to shift data from TDI to TDO, and an update latch operable to load data from the scan cell.
If selected by the instruction in the instruction register, gates – within gating circuit will be enabled by a signal on bus to couple the TAP’s CaptureDR state, ShiftDR state, and UpdateDR outputs to data register 2 ‘s Capture- 2 stancard, Shift- 2and Update- 2 inputs, respectively. This enables ieeee access of data register 2. The Stansard 2 input of standatd register 2 is coupled ieeee the free running TCK. If data register 2 is in test mode, the Mode- 2 input from instruction register bus will be set to cause the data in update latch to be output from data register The data registerreferred to as data register 3is an example of a gated scan data register that could be used as an internal scan path of a core or IC.
Data register 3 comprises serially connected conventional scan cells each operable standarx capture data from the IN input and to shift data from TDI to TDO.
If selected by the instruction in the instruction register, multiplexers – within gating circuit are enabled by a signal on bus to couple the TAP’s ClockDR and ShiftDR outputs to data register 3 ‘s Clock- 3 and Shift- 3 inputs, respectively.
Multiplexers – are used instead of gates since switching between a functional and test p150 and between functional iree test modes is required when using scan cells that are shared for functional and test operations.
This enables scan access of data register 3. The data registerreferred to as data register 4is an example of a synchronous scan data register that could be used as an internal scan path of a core or IC.
If selected by the instruction in the instruction register, multiplexers – within gating circuit will be enabled by a signal on bus to couple the TAP’s CaptureDR state output, the TAP’s ShiftDR state output, and the Stansard to data register 4 ‘s Capture- 4Shift- 4and Clock- 4 inputs, respectively. Again, multiplexers – are used instead of gates since switching between a functional and test clocks and between functional and test modes is required when using scan cells that are shared iees functional and test operations.
This enables scan access of data register 4. This standard test interface and architecture is being developed for the purpose of testing cores within ICs. While not yet standardized, the state of the P standard is stable and near complete. The architecture includes a wrapper instruction register and a set of selectable wrapper data registers. The WSP receives clock, capture, shift, update, transfer, select, and reset input signals.
The WSP responds to these signals to shift data through either the wrapper instruction register or a selected wrapper data register from the wrapper serial input WSI signal to the wrapper serial output WSO signal.
For the purpose of simplifying the following description, it will be assumed that the IEEE P architecture can be viewed as being the same as the previously described IEEE While there may be subtle differences between the two architectures, these differences are transparent to the overall objective of the present disclosure.
As seen, a gating circuit receives input from the instruction register to allow the data register control bus from the WSP to pass through the isee circuit and be output on bus to operate the selected data register. As mentioned, the WSP is a combinational circuit and does not include any sequential memory eiee. The operation of the WSP is simple. An example of their use will be described later in regard to FIGS. The dotted line clock pulses shown on portions of the inactive clock input signal indicates TCKs that would be input to the TAP during the instruction register scan timing diagram of FIG.
Being able to p1500 TAP instructions and, as will be shown below, data register scan timing is important since it provides for serially connecting the IEEE Again, the dotted line clock pulses shown standadr portions of the inactive clock input signal indicates TCKs that would be input to the TAP during the data register scan timing diagram of FIG. For example, in FIG. Data register 5, is comprised of a plurality of serially connected scan cellseach capable of performing shift and stwndard operations.
As seen, the scan cell circuit example consists of an input multiplexera series of flip stanardand an output multiplexer Gates and of gating circuit are enabled by signal to couple the ClockDR and TransferDR outputs from the WSP to the Clock- 5 and Transfer- 5 inputs to data register 5respectively, when a transfer instruction is loaded into the instruction register.
A pair of Mode-5 signals, Mode- 5 a and 5 bare output from the instruction register on bus to control the scan cell output multiplexers During transfer operations, the output multiplexers of scan cells that output test signals will be controlled to couple the output of the flip flops to the output multiplexer output OUTwhile the output multiplexers iede scan cells that input test signals will be controlled to couple the input IN of the scan cell to the output OUT of output multiplexers Thus two separately controllable Mode-5 signals, Mode- 5 a and 5 bwill typically be required from the instruction register to achieve a desired output multiplexer test setting.
The dotted line beginning at the TDI input of cell A and ending at the TDO oeee of cell C indicates the process of shifting data through the cells to load test input data to cells A and B sandard unload test output data from cell C.
As seen, the shifting occurs in response to Shift- 5 being high, Transfer- 5 being low, and Clock- 5 being active. While for simplicity the example of FIG. As seen, the transfer mode occurs in response to Shift- 5 being low, Transfer- 5 being high, and Clock- 5 being active.
During transfer mode, cells A and B circulate their data, as shown in dotted line, from the output OUT of their output multiplexers to the input of their input multiplexers, to provide stanvard test signal input to AND gate Simultaneously, cell C shifts in the etandard signal output from AND gateagain as shown in dotted line. The Mode- 5 a and Mode- 5 b inputs to the cell output multiplexers have been set, as previously described, for this particular transfer test arrangement.
The first transfer test session tests the AND gate’s ability to pass a stream of data from its In 1 input to its Out output, while its In 2 input is high. The second transfer test session tests the AND gate’s ability to pass a stream of data from its In 2 input to its Out output, while its In 1 input is high.
Firstly, the cells A-C are shifted, during time frameto load the test input patterns to be applied during the first transfer test session of FIG. Secondly, the first transfer test session of FIG. Thirdly, the cells A-C are shifted, during time frame to load the test input patterns to be applied during the second transfer test session of FIG. Fourthly, the second transfer session of FIG. Lastly, the cells A-C are shifted, during time frame to unload the test results of the second transfer test session.
While the above description has provided one detailed example of how an IEEE P transfer test may be performed, there are numerous other ways of designing and operating scan cells to achieve transfer testing.
The circuit is shown including both TAP based standards The architecture includes a commonly shared instruction registera commonly shared set of selectable data registerscommonly shared gating circuitryand commonly shared instruction and data control buses to the commonly shared TAP Regardless of whether circuit is a core or an IC, these 5 signals are dedicated and reserved for use in accessing the TAP to perform testing or other operations with the common architecture The availability of the dedicated TAP test bus has proven very beneficial since it provides non-intrusive access to a functionally operating circuit to perform real time test, emulation, debug, and other operations.
The dedicated TAP test bus has also lead to an ever increasing set of TAP interface support tools supporting test, emulation, debug, programming, and other TAP based operations. Therefore the IEEE P architecture is forced to include its own instruction registerits own set of selectable data registersits own gating circuitryand its own instruction and data control buses to WSP The primary reason for this forced separation is due to the differences in operation between the TAP and WSP interfaces.
If circuit is a core, these 9 signals will be dedicated terminals of the core. However, if circuit is an IC, these 9 signals are not required to be dedicated ICs pins, as are the TAP pinsand will typically be shared with functional pins on the IC and invoked only when testing of the IC is required.
If they are shared it is not possible to use them for real time test, emulation, debug, or other operations that can be used with the TAP and its dedicated test bus However, since improved testing of core based ICs is the primary objective of IEEE P that limitation will not matter, especially since TAP based solutions already exist for these expanded needs.
If the circuit is a core for use in an IC it will require a 5 signal bus for interfacing to the TAP and a 9 signal bus for interfacing to the WSP The total number of signals therefore that need to be routed in the IC for connection to core is In some ICs the routing of 14 test signals to a core can be prohibitive, especially if multiple cores exist with each potentially needing its own bus of 14 test signals.